In SMAs (shared memory architecture), data and program partitioning is typically carried out by placing data requiring processing by multiple threads into the shared memory and splitting program more independently to processors, thus making programming easier compared to message passing (MPA) architectures in which processing happens always locally and the programmer is responsible for moving data around accordingly. Unfortunately most SMAs use a distributed shared memory architecture consisting of multiple interconnected processor-cache pairs, which makes cache coherency (and therefore latency tolerance) and synchronicity maintenance very expensive. This may even ruin their performance in communication intensive problems.
To tackle e.g. the above problem, the emulated shared memory (ESM), or shared memory emulation, architectures have been introduced. They incorporate a set of multithreaded processors that are connected via a high-throughput intercommunication network to a common uniformly and synchronously accessible shared memory. The memory system latency is hidden by overlapping on-going memory references and a special low-cost synchronization mechanism is established guaranteeing synchronicity at machine instruction level. The ESM systems provide the user with perception of ideal shared memory even though the actual hardware architecture comprises a physically distributed memory. From a theoretical standpoint, these architectures attempt to emulate the abstract parallel random access machine (PRAM) that is commonly used as a model for describing and analyzing the intrinsic parallelism of computational problems as well as performance and cost of executing parallel algorithms due to its simplicity and expressivity. A PRAM model generally refers to a set of processors working under the same clock and a uniform single step accessible shared memory connected to them.
Accordingly, ESM is a feasible technique to address programmability and performance scalability concerns of chip multiprocessors (CMP) as it yields implied synchrony in the execution of machine instructions, efficient latency hiding technique, and sufficient bandwidth to route all the memory references even with heavy random and concurrent access workloads. Synchronous execution is considered to make programming easier as a programmer does not need to synchronize the threads of execution explicitly after each global memory access but can rely on the hardware to take care of that automatically, whereas e.g. in message passing architectures (MPA), a programmer is responsible for explicitly defining communication, synchronizing subtasks, and describing data and program partitioning between threads making MPAs difficult to program. Latency hiding used in shared memory emulation makes use of the high-throughput computing scheme, where other threads are executed while a thread refers to the global shared memory. Since the throughput computing scheme employs parallel slackness extracted from the available thread-level parallelism, it is considered to provide enhanced scalability in contrast to traditional symmetric multiprocessors and non-uniform memory access (NUMA) systems relying on snooping or directory-based cache coherence mechanisms and therefore suffering from limited bandwidth or directory access delays and heavy coherence traffic maintenance.
Recently, scalable ESM architectures have been suggested incorporating step caches to implement the concurrent read concurrent write (CRCW) memory access variant of PRAM, which further simplifies programming and increases performance by a logarithmic factor in certain cases. Also a mechanism to support constant execution time multi(-prefix)operations—implementing even stronger multioperation concurrent read concurrent write (MCRCW) variant of the PRAM model—has been implemented with the help of scratchpads that are attached to step caches in order to bound the associativity of step caches. For instance, publications 1: M. Forsell, Step Caches—a Novel Approach to Concurrent Memory Access on Shared Memory MP-SOCs, In the Proceedings of the 23th IEEE NORCHIP Conference, Nov. 21-22, 2005, Oulu, Finland, 74-77, 2: M. Forsell, Reducing the associativity and size of step caches in CRCW operation, In the Proceeding of 8th Workshop on Advances in Parallel and Distributed Computational Models (in conjunction with the 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS'06), Apr. 25, 2006, Rhodes, Greece, 3: M. Forsell, Realizing Multioperations for Step Cached MP-SOCs, In the Proceedings of the International Symposium on System-on-Chip 2006 (SOC'06), Nov. 14-16, 2006, Tampere, Finland, 77-82., 4: M. Forsell, TOTAL ECLIPSE—An Efficient Architectural Realization of the Parallel Random Access Machine, In Parallel and Distributed Computing Edited by Alberto Ros, INTECH, Vienna, 2010, 39-64., and 5: M. Forsell and J. Roivainen, Supporting Ordered Multiprefix Operations in Emulated Shared Memory CMPs, In the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'11), Jul. 18-21, 2011, Las Vegas, USA, 506-512, contemplate different aspects of such a solution and are thereby incorporated herein by reference in their entireties. Multi(-prefix)operations can be defined for many basic operations, e.g. ADD, SUB, MAX etc., and considered as parallel primitives due to the capability to express parallel algorithms. They can be used for synchronization and parallel data structures simultaneously accessed by several processors without race conditions and other anomalies of architectures executing threads asynchronously.
In FIG. 1, a high-level illustration of a scalable architecture to emulate shared memory on a silicon platform is shown. It comprises a set of processors (cores) P1, P2, P3, . . . , Pp 102 connected to a physically distributed, but logically shared (data) memory M1, M2, M3, . . . , Mp 112 via a physically scalable high bandwidth interconnection network 108. Active memory units 110 in connection with data memory 112 can be considered as memory control logic units utilized to process the memory references. The active memory units 110 are arranged to manage computation related to cases in which multiple memory references are targeted to the same memory location during e.g. multi(-prefix) operations, for instance. Instruction memory modules I1, I2, I3, . . . , Ip 104 are configured to carry the program code for each processor 102. To efficiently emulate shared memory by the distributed memory-based implementation, the processors 102 are multithreaded utilizing a Tp-stage cyclic, interleaved inter-thread pipeline (Tp≥the average latency of the network). The PRAM model is linked to the architecture such that a full cycle in the pipeline corresponds typically to a single PRAM step. During a step of multi-threaded execution (regarding the pipeline in overall, i.e. all pipeline stages including the actual execution stage), each thread of each processor of the CMP executes an instruction including at most one shared memory reference sub-instruction. Therefore a step lasts for multiple, at least Tp+1 clock cycles.
In the depicted architecture, step caches are generally associative memory buffers in which data stays valid only to the end of ongoing step of multithreaded execution. The main contribution of step caches to concurrent accesses is that they step-wisely filter out everything but the first reference for each referenced memory location. This reduces the number of requests per location from P Tp down to P allowing them to be processed sequentially on a single ported memory module assuming Tp≥P. Scratchpads are addressable memory buffers that are used to store memory access data to keep the associativity of step caches limited in implementing multioperations with the help of step caches and minimal on-core and off-core ALUs (arithmetic logic unit) that take care of actual intra-processor and inter-processor computation for multioperations. Scratchpads may be coupled with step caches to establish so-called scratchpad step cache units S1, S2, S3, . . . , Sp 106.
One underlying idea of the reviewed solution is indeed in the allocation of each processor core 102 with a set of threads that are executed efficiently in an interleaved manner and hiding the latency of the network. As a thread makes a memory reference, the executed thread is changed and the next thread can make its memory request and so on. No memory delay will occur provided that the reply of the memory reference of the thread arrives to the processor core before the thread is put back to execution. This requires that the bandwidth of the network is high enough and hot spots can be avoided in pipelined memory access traffic. Synchronicity between consecutive instructions can be guaranteed by using an elastic synchronization wave between the steps, for instance.
FIG. 2 shows, at 200, one illustration of an ESM CMP architecture incorporating e.g. the aforementioned active memory units 112B (with ALU and fetcher) in connection with data memory modules 112 and scratchpads 206B. The network 108 may be a mesh-like interconnection network acting as a high-bandwidth pipelined memory system with switches 108B. The memory access latency is hidden by executing other threads while a thread is referencing the uniformly accessible distributed shared memory via the network 108. Congestion of references and hot spots in communication can be avoided with an efficient dead-lock free intercommunication architecture featuring high bandwidth (bisection BW≥P/4) and randomized hashing of memory locations over the distributed memory modules. Execution of instructions happens in steps corresponding to a single PRAM step during which each thread executes a single instruction.
Despite of the many aforementioned advantages, ESM systems have appeared difficult to realize in truly optimal fashion. A physically feasible memory unit (MU) making use of step cache and scratchpad techniques to support strong concurrent memory access and multi(-prefix)operations is easily comprehensible as one key component of powerful emulated shared memory architecture like REPLICA (REmoving Performance and programmability LImitations of Chip multiprocessor Architectures), which is basically a configurable ESM. Such MU may be configured to send the outgoing memory references to the shared memory system as well as wait and receive possible replies therefrom, for example.
FIG. 3 represents, at 300, a high-level block diagram and pipeline of a typical MCRCW ESM processor making use of e.g. step caches. A processor in a step cache-based MCRCW (C)ESM CMP comprises A ALUs, M memory units (MU), a distributed or unified register block, a sequencer and some glue logic. In the figure Ax 302 refers to ALU x, IF 308 refers to instruction fetch logic, MEM 304 refers to memory unit stage, OS 306 refers to operand selection logic and SEQ 310 refers to sequencer. As implied in the figure, there are ALUs 302 logically positioned prior to and after the memory unit wait segment.
Generally, integer-based arithmetic operations taken care of by ALUs in the modern processor architectures include addition, subtraction, multiplication and division. Further, the ALUs are often responsible for performing logical operations that may incorporate comparing e.g. two data elements to each other to sort out which was smaller/bigger or whether they were equal, and making related decisions based on the outcome of such comparisons.
Yet, specialized functional units may be allocated for executing certain specific tasks and operations involving calculations of particular complexity, for instance. Execution of such complex or otherwise special operations could require additional logic or hardware, and take a greater number of clock cycles or generally just take longer, i.e. cause a longer latency, to complete in contrast to e.g. basic ALU operations.
In processor architectures, several parallel processing paths may be provided, each potentially provided with special purpose or specific task to be performed using the hardware disposed on that particular path. Nevertheless, the latency caused by the associated elements and related processing taking place in the paths often adds to the overall execution time of instructions proceeding in the processor pipeline structure.